systolic-arrays-explained

Systolic Arrays Explained

How the hardware multiplies matrices

A matrix unit is a grid of multiply-accumulate cells that pass numbers to their neighbours every clock cycle: each operand is fetched from memory once and used by a whole row or column of cells. This site takes that machine apart one cycle at a time: which operand stays put, how the inputs are skewed so everything meets at the right moment, and where the cycles go.

Every animation is drawn from a cycle-accurate model of the array (Python reference, exact TypeScript port). Its output-stationary frames match a SystemVerilog array simulated in Verilator on every accumulator after every clock edge: 613 values, 0 mismatches.

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The model, its conventions and the RTL cross-check: the model.

Part of a family of companion sites: the Transformer Decoder Explainer (one forward pass), LLM Inference Explained (serving it), LLM Architectures Explained (how the models differ), GPU Kernels Explained (how a GPU runs the maths) and Numerics Explained (the number formats). This site is the silicon underneath. How it was built, and how to check it: about.